Method for forming shielded gate field effect transistor using spacers
US7935577B2 · kind B2 · utility
7Cited by
8References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2008 |
| Grant date | May 3, 2011 |
| Priority date | — |
| Expiry date | Mar 23, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A trench is formed in a semiconductor region. A dielectric layer lining sidewalls and bottom surface of the trench is formed. The dielectric layer is thicker along lower sidewalls and the bottom surface than along upper sidewalls of the trench. After forming the dielectric layer, a lower portion of the trench is filled with a shield electrode. Dielectric spacers are formed along the upper trench sidewalls. After forming the dielectric spacers, an inter-electrode dielectric (IED) is formed in the trench over the shield electrode. After forming the IED, the dielectric spacers are removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.