Epitaxially coated silicon wafer and method for producing epitaxially coated silicon wafers

US7935614B2 · kind B2 · utility

Assignee

• Siltronic AG · DE

Inventors

• Reinhard Schauer · Laufen, DE
• Norbert Werner · Dodge City, US

Key dates

• Filing date: Jun 29, 2009
• Grant date: May 3, 2011
• Expiry date: Jun 29, 2029

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/905
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A multiplicity of silicon wafers polished at least on their front sides are provided and successively coated individually in an epitaxy reactor by a procedure whereby one of the wafers is placed on a susceptor in the epitaxy reactor, is pretreated under a hydrogen atmosphere at a first hydrogen flow rate, and with addition of an etching medium to the hydrogen atmosphere at a reduced hydrogen flow rate in a second step, is subsequently coated epitaxially on its polished front side, and removed from the reactor. An etching treatment of the susceptor follows a specific number of epitaxial coatings. Silicon wafers produced thereby have a global flatness value GBIR of 0.07-0.3 μm relative to an edge exclusion of 2 mm.