On-chip interconnect-stack cooling using sacrificial interconnect segments
US7936563B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2006 |
| Grant date | May 3, 2011 |
| Priority date | — |
| Expiry date | May 1, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to an integrated-circuit device and to a method for fabricating an integrated-circuit device with an integrated fluidic-cooling channel. The method comprises forming recesses in a dielectric layer sequence at desired lateral positions of electrical interconnect segments and at desired lateral positions of fluidic-cooling channel segments. A metal filling is deposited in the recesses of the dielectric layer sequence so as to form the electrical interconnect segments and to form a sacrificial filling in the fluidic-cooling channel segments. Afterwards, the sacrificial metal filling is selectively removed from the fluidic-cooling channel segments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.