Receiver of semiconductor memory apparatus
US7936620B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2009 |
| Grant date | May 3, 2011 |
| Priority date | — |
| Expiry date | Oct 28, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A receiver of a semiconductor memory apparatus includes a first input transistor configured to be turned ON when an input signal is equal to or more than a predetermined level; a second input transistor configured to be turned ON when the input signal is equal to or less than the predetermined level; a first output node voltage control unit configured to increase a voltage level of an output node when the first input transistor is turned ON; a second output node voltage control unit configured to decrease the voltage level of the output node when the second input transistor is turned ON; a third input transistor configured to increase the voltage level of the output node when an inversion signal of the input signal is equal to or less than the predetermined voltage level; and a fourth input transistor configured to decrease the voltage level of the output node when the inversion signal of the input signal is equal to or more than the predetermined voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.