Reduced power bitline precharge scheme for low power applications in memory devices
US7936624B2 · kind B2 · utility
16Cited by
2References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 27, 2007 |
| Grant date | May 3, 2011 |
| Priority date | — |
| Expiry date | Jan 13, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system are described for a two step precharging of bitlines in a memory array. In the first step a partial precharge of the bitline is accomplished with a lower power supply, the second step completes the bitline precharge with the higher power supply. Since the higher power supply must ultimately supply the final bitline precharge voltage achieving a partial bitline precharge with a lower power supply will result in lower sram and system power.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.