Precise counter hardware for microcode loops
US7937574B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2007 |
| Grant date | May 3, 2011 |
| Priority date | — |
| Expiry date | Jul 7, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a microcode unit for a processor is contemplated. The microcode unit comprises a microcode memory storing a plurality of microcode routines executable by the processor, wherein each microcode routine comprises two or more microcode operations. Coupled to the microcode memory, the sequence control unit is configured to control reading microcode operations from the microcode memory to be issued for execution by the processor. The sequence control unit is configured to stall issuance of microcode operations forming a body of a loop in a first routine of the plurality of microcode routines until a loop counter value that indicates a number of iterations of the loop is received by the sequence control unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.