Patent · US Active

System and method for integrated circuit planar netlist interpretation

US7937678B2 · kind B2 · utility

30Cited by

15References

27Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Bernhard Lippmann · Landshut, DE
Andreas Junghanns · Falkensee, DE

Key dates

Filing date	Jun 11, 2008
Grant date	May 3, 2011
Priority date	—
Expiry date	Jul 30, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/327
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Systems and methods for integrated circuit planar netlist interpretation are disclosed. In one embodiment, higher abstraction level descriptions of an integrated circuit are generated from a planar netlist and layout data of the integrated circuit. Various embodiments may derive the higher abstraction levels through, for example, netlist compression and netlist partitioning. Other embodiments may derive the higher abstraction levels using, for example, device and module hypothesis search functions based on device properties and design constraints derived from netlist and layout data.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.