Systems and methods that selectively modify liner induced stress
US7939400B2 · kind B2 · utility
0Cited by
7References
9Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 23, 2008 |
| Grant date | May 10, 2011 |
| Priority date | — |
| Expiry date | Jan 22, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided (102). A strain inducing liner is formed over the semiconductor device (104). A selection mechanism, such as a layer of photoresist or UV reflective coating is applied to the semiconductor device to select a region (106). The selected region is treated with a stress altering treatment that alters a type and/or magnitude of stress produced by the selected region (108).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.