Method for manufacturing nonvolatile semiconductor memory device structure

US7939423B2 · kind B2 · utility

Assignee

• EON Silicon Solution Inc. · TW

Inventor

• Yider Wu · Campbell, US

Key dates

• Filing date: Apr 16, 2010
• Grant date: May 10, 2011
• Expiry date: Apr 16, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B69/00

Abstract

A non-volatile semiconductor manufacturing method comprises the steps of making element isolation/insulation films that partitions element-forming regions in a semiconductor substrate; stacking a floating gate on the semiconductor substrate via a first gate insulating film; stacking a second gate insulating film formed on the floating gate, and stacking a control gate formed on the floating gate via the second gate insulating film, and self-aligning source and drain diffusion area with the control gate. In the process of stacking a floating gate by partially etching a field oxide film in a select gate area, followed by floating gate formed in a element-forming region and select gate region, and followed by a chemical mechanical polish(CMP) process, both floating gate and select gate is hereby formed simultaneously. Thereby, when memory cells are miniaturized, the invention allows the process to be simple and reduce the defect density.