Patent · US Active

Area efficient 3D integration of low noise JFET and MOS in linear bipolar CMOS process

US7939863B2 · kind B2 · utility

5Cited by
3References
19Claims
0Family size

Assignee

Inventors

Key dates

Filing dateAug 7, 2009
Grant dateMay 10, 2011
Priority date—
Expiry dateDec 23, 2029

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D86/201
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Analog ICs frequently include circuits which operate over a wide current range. At low currents, low noise is important, while IC space efficiency is important at high currents. A vertically integrated transistor made of a JFET in parallel with an MOS transistor, sharing source and drain diffused regions, and with independent gate control, is disclosed. N-channel and p-channel versions may be integrated into common analog IC flows with no extra process steps, on either monolithic substrates or SOI wafers. pinchoff voltage in the JFET is controlled by photolithographically defined spacing of the gate well regions, and hence exhibits low variability.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.