Gate driver circuit for H bridge circuit
US7940092B2 · kind B2 · utility
9Cited by
14References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2009 |
| Grant date | May 10, 2011 |
| Priority date | — |
| Expiry date | Oct 10, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M7/538
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An H bridge circuit includes a gate driver circuit coupled to a gate of an NMOS device. The output of the gate driver circuit is at a voltage from 0.1V to 0.4V during a dead time of the H bridge circuit. The gate voltage of the NMOS device is biased at 0.1˜0.4V to overcome the problems of minority carrier injection and power dissipation as compared with VG=0 in a conventional H bridge circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.