Method for low power sensing in a multi-port SRAM using pre-discharged bit lines
US7940581B2 · kind B2 · utility
8Cited by
6References
10Claims
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Key dates
| Filing date | Aug 23, 2010 |
| Grant date | May 10, 2011 |
| Priority date | — |
| Expiry date | Aug 23, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for sensing the contents of a memory cell within a static random access memory (SRAM) includes holding a bit line associated with the memory cell at a zero voltage potential when the memory cell is not being accessed; energizing the bit line to a first voltage potential different than the zero voltage potential during an access of the memory cell; and sensing the memory cell contents when the associated bit line has reached the first voltage potential.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.