Multi-column decoder stress test circuit
US7940585B2 · kind B2 · utility
1Cited by
2References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 7, 2008 |
| Grant date | May 10, 2011 |
| Priority date | — |
| Expiry date | Feb 25, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/2602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The embodiments described herein are directed to providing a multi-column decoder stress test circuit capable of reducing a column stress test time while sufficiently performing a stress test by using column selection signals. The multi-column decoder stress test circuit comprising a control unit configured to receive at least one column test signal and to generate a multi-column enable signal, and a multi-enable decoding unit configured to receive the multi-column enable signal and to generate a plurality of enabled column selection signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.