Local scratchpad and data caching system
US7941585B2 · kind B2 · utility
13Cited by
63References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2004 |
| Grant date | May 10, 2011 |
| Priority date | — |
| Expiry date | Dec 17, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A RISC-type processor includes a main register file and a data cache. The data cache can be partitioned to include a local memory, the size of which can be dynamically changed on a cache block basis while the processor is executing instructions that use the main register file. The local memory can emulate as an additional register file to the processor and can reside at a virtual address. The local memory can be further partitioned for prefetching data from a non-cacheable address to be stored/loaded into the main register file.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.