Method and apparatus for high reliability data storage and retrieval operations in multi-level flash cells
US7941592B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Aug 14, 2008 |
| Grant date | May 10, 2011 |
| Priority date | — |
| Expiry date | Oct 24, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One or more multi-level NAND flash cells are operated so as to store only single-level data, and these operations achieve an increased level of charge separation between the data states of the single-level operation by requiring a write to both the upper and lower pages, even though only one bit of data is being stored. That is, the second write operation increases the difference in floating gate charge between the erased state and the programmed state of the first write operation without changing the data in the flash memory cell. In one embodiment, a controller instructs the flash memory to perform two write operations for storing a single bit of data in an MLC flash cell. In another embodiment, the flash memory recognizes that a single write operation is directed a high reliability memory area and internally generates the required plurality of programming steps to place at least a predetermined amount of charge on the specified floating gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.