Specialized memory move barrier operations
US7941627B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2008 |
| Grant date | May 10, 2011 |
| Priority date | — |
| Expiry date | Jun 14, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30087
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An instruction set architecture (ISA) includes an asynchronous memory move (AMM) synchronization (SYNC) instruction. When processor of a data processing system executes the AMM SYNC instruction, the processor prevents an AMM operation generated by a subsequently received/executed AMM ST instruction from proceeding with the data move portion of the AMM operation within the memory subsystem until completion of all ongoing memory access operations within the memory subsystem and fabric. The AMM operation does not wait for a normal barrier operation. The processor forwards the information relevant to initiate the AMM operation to an asynchronous memory mover logic, and signals the logic to not proceed with the AMM operation until signaled of the completion of the AMM SYNC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.