Method for computing power savings and determining the preferred clock gating circuit of an integrated circuit design
US7941679B2 · kind B2 · utility
5Cited by
10References
22Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 10, 2007 |
| Grant date | May 10, 2011 |
| Priority date | — |
| Expiry date | Jan 20, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for computing the power savings in an integrated circuit (IC) design is disclosed. The method computes the difference in power savings between techniques used for clock gating. Based on the computation results, the method outputs a script to control the implementation tool so as to provide for the best implementation clock gating technique in terms of power and area savings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.