Asymmetric junction field effect transistor

US7943445B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Frederick G. Anderson · South Burlington, US
• David S. Collins · Thousand Oaks, US
• Richard A. Phelps · Colchester, US
• Robert M. Rassel · Colchester, US
• Michael J. Zierak · Colchester, US

Key dates

• Filing date: Feb 19, 2009
• Grant date: May 17, 2011
• Expiry date: Aug 15, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/86

Abstract

A junction field effect transistor (JFET) in a semiconductor substrate includes a source region, a drain region, a channel region, an upper gate region, and a lower gate region. The lower gate region is electrically connected to the upper gate region. The upper and lower gate regions control the current flow through the channel region. By performing an ion implantation step that extends the thickness of the source region to a depth greater than the thickness of the drain region, an asymmetric JFET is formed. The extension of depth of the source region relative to the depth of the drain region reduces the length for minority charge carriers to travel through the channel region, reduces the on-resistance of the JFET, and increases the on-current of the JFET, thereby enhancing the overall performance of the JFET without decreasing the allowable Vds or dramatically increasing Voff/Vpinch.