Minimum cost method for forming high density passive capacitors for replacement of discrete board capacitors using a minimum cost 3D wafer-to-wafer modular integration scheme
US7943473B2 · kind B2 · utility
10Cited by
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40Claims
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Key dates
| Filing date | Jan 13, 2009 |
| Grant date | May 17, 2011 |
| Priority date | — |
| Expiry date | Aug 16, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Passive, high density, 3d IC capacitor stacks and methods that provide the integration of capacitors and integrated circuits in a wafer to wafer bonding process that provides for the integration of capacitors formed on one wafer, alone or with active devices, with one or more integrated circuits on one or more additional wafers that may be stacked in accordance with the process. Wafer to wafer bonding is preferably by thermo-compression, with grinding and chemical mechanical polishing being used to simply aspects of the process of fabrication. Various features and alternate embodiments are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.