Transistor with a plurality of layers with different Ge concentrations
US7943969B2 · kind B2 · utility
12Cited by
0References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2008 |
| Grant date | May 17, 2011 |
| Priority date | — |
| Expiry date | Aug 4, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
Abstract
A transistor and a method of fabricating the same are provided. The transistor includes a SiGe epitaxial layer formed in a recess region of a substrate at both side of a gate electrode and a SiGe capping layer formed on the SiGe epitaxial layer. The transistor further includes a SiGe seed layer formed under the SiGe epitaxial layer and a silicon capping layer formed on the SiGe capping layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.