Methods of fabricating transistors having buried P-type layers coupled to the gate
US7943972B2 · kind B2 · utility
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14Claims
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Key dates
| Filing date | Nov 30, 2009 |
| Grant date | May 17, 2011 |
| Priority date | — |
| Expiry date | Nov 30, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/343
Abstract
A unit cell of a metal-semiconductor field-effect transistor (MESFET) is provided. The MESFET has a source, a drain and a gate. The gate is between the source and the drain and on an n-type conductivity channel layer. A p-type conductivity region is provided beneath the gate between the source and the drain. The p-type conductivity region is spaced apart from the n-type conductivity channel layer and electrically coupled to the gate. Related methods are also provided herein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.