Method and apparatus for detecting clock loss
US7944261B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2007 |
| Grant date | May 17, 2011 |
| Priority date | — |
| Expiry date | Feb 18, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for detecting clock loss in clock circuit. An example of the invention relates to detecting loss of a feedback clock signal input to a digital clock manager, where the feedback clock signal is derived from the reference clock signal. A clock divider is provided to produce a divided feedback clock signal from the feedback clock signal. A first pair of flip-flops is configured to store samples of the divided feedback clock signal on consecutive edges of the reference clock signal. A second pair of flip-flops is configured to store samples of the divided feedback clock signal on consecutive edges of an inversion of the reference clock signal. Detection logic is configured to detect whether each of the first pair of flip-flops and each of the second pair of flip-flops store the same value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.