Clock generator, method for generating clock signal and fractional phase lock loop thereof
US7944265B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2008 |
| Grant date | May 17, 2011 |
| Priority date | — |
| Expiry date | Mar 25, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/16
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock generator includes a delta sigma modulator, a counter and a first phase lock loop. The delta sigma modulator sequentially generates a plurality of variable parameters according to a predetermined value and a first input clock signal. The counter, which is connected to the delta sigma modulator, is used to generate an output clock signal in accordance with a counting value and a second input clock signal. The counting value is relevant to the variable parameters. The first phase lock loop, which is connected to the output of the counter, is used to generate an objective clock signal in accordance with the output clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.