Methods and systems for reusing memory addresses in a graphics system
US7944452B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2006 |
| Grant date | May 17, 2011 |
| Priority date | — |
| Expiry date | Jun 27, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems for reusing memory addresses in a graphics system are disclosed, so that instances of address translation hardware can be reduced. One embodiment of the present invention sets forth a method, which includes mapping a footprint in screen space to a group of contiguous physical memory locations in a memory system, determining a first physical memory address for a first transaction associated with the footprint, wherein the first physical memory address is within the group of contiguous physical memory locations, determining a second transaction that is also associated with the footprint, determining a set of least significant bits associated with the second transaction, and combining a portion of the first physical memory address with the set of least significant bits associated with the second transaction to generate a second physical memory address for the second transaction, thereby avoiding a second full address translation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.