Multi-node computer system employing a reporting mechanism for multi-node transactions
US7945738B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 9, 2004 |
| Grant date | May 17, 2011 |
| Priority date | — |
| Expiry date | Nov 25, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/507
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system may include a node and an additional node coupled by an inter-node network. The node includes an active device, an interface to the inter-node network, a memory, and an address network coupling the active device, the interface, and the memory. The active device sends an address packet to initiate a transaction to gain an access right to a coherency unit. In response to receiving the address packet, the memory is configured to send a report corresponding to the address packet to the interface if the transaction cannot be satisfied within the node. The interface is configured to ignore the address packet and to send a coherency message requesting the access right to the additional node via the inter-node network in response to the report.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.