Patent · US Active

DRAM device having a gate dielectric layer with multiple thicknesses

US7948028B2 · kind B2 · utility

30Cited by
2References
6Claims
0Family size

Assignee

Inventor

Key dates

Filing dateMar 17, 2008
Grant dateMay 24, 2011
Priority date—
Expiry dateAug 24, 2028

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D84/856
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A transistor device employed in a support circuit of a DRAM includes a semiconductor substrate having thereon a gate trench, a recessed gate embedded in the gate trench, a source doping region disposed at one side of the recessed gate, a drain doping region disposed at the other side of the recessed gate, and a gate dielectric layer between the recessed gate and the semiconductor substrate. The gate dielectric layer has at least two thicknesses that render the high-voltage transistor device asymmetric. The thicker gate dielectric layer is between the recessed gate and the drain doping region, while the thinner gate dielectric layer is between the recessed gate and the source doping region.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.