Multiple-gate transistor structure and method for fabricating

US7948037B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Hao Chen
• Yee-Chia Yeo · Baoshan, TW
• Fu-Liang Yang · Baoshan, TW

Key dates

• Filing date: Apr 13, 2010
• Grant date: May 24, 2011
• Expiry date: Apr 13, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6213

Abstract

A multiple-gate transistor structure which includes a substrate, source and drain islands formed in a portion of the substrate, a fin formed of a semi-conducting material that has a top surface and two sidewall surfaces, a gate dielectric layer overlying the fin, and a gate electrode wrapping around the fin on the top surface and the two sidewall surfaces separating source and drain islands. In an alternate embodiment, a substrate that has a depression of an undercut or a notch in a top surface of the substrate is utilized.