Advanced memory device having reduced power and improved performance
US7948817B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2009 |
| Grant date | May 24, 2011 |
| Priority date | — |
| Expiry date | Jun 14, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device including a memory array storing data, a variable delay controller, a passive variable delay circuit and an output driver. The variable delay controller periodically receives delay commands from a first source external to the memory device during operation of the memory device, and outputs delay instruction bits responsive to the received delay commands. The passive variable delay circuit receives a clock from a second source external to the memory device, receives the delay instruction bits from the variable delay controller, generates a delayed clock having a time relation to the received clock as determined by the delay instruction bits, and outputting the delayed clock. The output driver receives the data from the memory array and the delayed clock, and outputs the data at a time responsive to the delayed clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.