Patent · US Active

Latency reduction for cache coherent bus-based cache

US7949832B2 · kind B2 · utility

3Cited by

5References

15Claims

0Family size

Assignee

Apple Inc. · US

Inventors

Brian P. Lilly · San Francisco, US
Sridhar Subramanian · Cupertino, US
Ramesh Gunna · San Jose, US

Key dates

Filing date	Mar 1, 2010
Grant date	May 24, 2011
Priority date	—
Expiry date	Mar 1, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F12/084
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In one embodiment, a system comprises a plurality of agents coupled to an interconnect and a cache coupled to the interconnect. The plurality of agents are configured to cache data. A first agent of the plurality of agents is configured to initiate a transaction on the interconnect by transmitting a memory request, and other agents of the plurality of agents are configured to snoop the memory request from the interconnect. The other agents provide a response in a response phase of the transaction on the interconnect. The cache is configured to detect a hit for the memory request and to provide data for the transaction to the first agent prior to the response phase and independent of the response.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.