Method and apparatus for setting cache policies in a processor
US7949834B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 24, 2007 |
| Grant date | May 24, 2011 |
| Priority date | — |
| Expiry date | Jan 4, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to the methods and apparatus taught herein, processor caching policies are determined using cache policy information associated with a target memory device accessed during a memory operation. According to one embodiment of a processor, the processor comprises at least one cache and a memory management unit. The at least one cache is configured to store information local to the processor. The memory management unit is configured to set one or more cache policies for the at least one cache. The memory management unit sets the one or more cache policies based on cache policy information associated with one or more target memory devices configured to store information used by the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.