Isolation verification within integrated circuits
US7949974B1 · kind B1 · utility
7Cited by
3References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2008 |
| Grant date | May 24, 2011 |
| Priority date | — |
| Expiry date | Aug 29, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method of verifying isolation between a plurality of modules of a circuit design to be implemented within an integrated circuit can include identifying a first module and at least a second module of the circuit design for the integrated circuit. One or more circuit attributes indicative of isolation between the first module and the second module can be identified and compared with at least one isolation criterion. An indication of whether the first module is isolated from the second module can be output according to results of the comparison.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.