Via density change to improve wafer surface planarity
US7949981B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 31, 2008 |
| Grant date | May 24, 2011 |
| Priority date | — |
| Expiry date | Jul 31, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Changing a via density for viafill vias to improve wafer surface planarity for later photolithography is provided, in one embodiment, by obtaining a circuit design including a plurality of viafill vias having differing via density across the circuit design, each viafill via interconnecting non-functional metal fill shapes in different layers of the circuit design; selecting a region of the circuit design to evaluate using an evaluation window; determining a via density within the evaluation window; and changing a number of viafill vias within the region in the circuit design in response to the via density being different than a threshold via density that is selected such that a coating deposited over the plurality of vias presents a substantially planar surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.