Performing die-to-wafer stacking by filling gaps between dies
US7951647B2 · kind B2 · utility
7Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2008 |
| Grant date | May 31, 2011 |
| Priority date | — |
| Expiry date | Jun 19, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19043
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit structure includes a bottom semiconductor chip; a top die bonded onto the bottom semiconductor chip; a protecting material encircling the bottom die and on the bottom semiconductor chip; and a planar dielectric layer over the top die and the protecting material. The protecting material has a top surface leveled with a top surface of the top die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.