Patent · US Active

Double exposure semiconductor process for improved process margin

US7951722B2 · kind B2 · utility

5Cited by
4References
14Claims
0Family size

Assignee

Inventor

Key dates

Filing dateAug 8, 2007
Grant dateMay 31, 2011
Priority date—
Expiry dateFeb 3, 2030

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG03F7/40
  • WIPO fieldOptics
  • WIPO sectorInstruments

Abstract

A double exposure semiconductor process is provided for improved process margin at reduced feature sizes. During a first processing sequence, features defining non-critical dimensions of a polysilicon interconnect structure are formed, while other portions of the polysilicon layer are left un-processed. During a second processing sequence, features that define the critical dimensions of the polysilicon interconnect structure are formed without the need to execute a photoresist trimming procedure. Accordingly, only an etch process is executed, which provides higher resolution processing to create the critical dimensions needed during the second processing sequence.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.