Semiconductor package and fabrication method thereof
US7952210B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2008 |
| Grant date | May 31, 2011 |
| Priority date | — |
| Expiry date | Sep 30, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19041
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There is provided a semiconductor package comprising: a multilayer thin film structure including a plurality of dielectric layers and at least one or more redistribution layers; a semiconductor chip positioned at one side of the multilayer thin film structure and electrically connected to the redistribution layer; and a solder bump formed at the other side of the multilayer thin film structure. The multilayer thin film structure functions as the substrate for the semiconductor package and realizes the light, thin, short and small BGA package without any additional substrate. A plurality of the packages can be simultaneously formed at wafer level or carrier level, to simplify the process and to be favorable for mass production. After the semiconductor chips are formed at wafer level, only the semiconductor chips having the excellent operation characteristic through the test are selectively bonded to the multilayer thin film structure, to provide the high quality package products in which the fault rate is maximally reduced. The light, thin, short and small BGA package according to the present invention enables small and slim communication devices, displayers and other diverse electr…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.