Tunable stress technique for reliability degradation measurement
US7952378B2 · kind B2 · utility
4Cited by
6References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2009 |
| Grant date | May 31, 2011 |
| Priority date | — |
| Expiry date | Jan 23, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2856
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Apparatus and methods are disclosed for examining how reliability in an RF power amplifier circuit changes as a function of variation of the input to output voltage swings. Two output transistors that varying greatly in the size of their respective channel widths are provided for independently evaluating impacts on the output waveform. The gate control for the smaller transistor is separate from the gate control to the larger transistor. The gate and drain stress can thus be adjusted and evaluated independently.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.