Process/design methodology to enable high performance logic and analog circuits using a single process

US7952423B2 · kind B2 · utility

Assignee

• Altera Corporation · US

Inventors

• Qi Xiang · San Jose, US
• Albert Ratnakumar · San Jose, US
• Jeffrey Tung · Milpitas, US
• Weiqi Ding · Fremont, US

Key dates

• Filing date: Sep 30, 2008
• Grant date: May 31, 2011
• Expiry date: Sep 30, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0227
• WIPO field: Control
• WIPO sector: Instruments

Abstract

A method for improving analog circuits performance using a circuit design using forward bias and a modified mixed-signal process is presented. A circuit consisting plurality of NMOS and PMOS transistors is defined. The body terminal of the NMOS transistors are coupled to a first voltage source and the body terminal of the PMOS transistors are coupled a second voltage source. Transistors in the circuit are selectively biased by applying the first voltage source to the body terminal of each selected NMOS transistor and applying the second voltage source to the body terminal of each selected PMOS transistor. In one embodiment, the first voltage source and the second voltage source are modifiable to provide forward and reverse bias to the body terminal of the transistors.