Inventor · San Jose, CA, US

Qi Xiang

205Patents
35h-index
90Co-inventors
93Inventor score

Filing activity: Oct 31, 1997 → Jun 29, 2021

Most-cited inventions

PatentTitleAreaCited byStatus
US6682973B1 Formation of well-controlled thin SiO, SiN, SiON layer for multilayer high-K dielectric applications Electricity 547 Expired
US7071051B1 Method for forming a thin, high quality buffer layer in a field effect transistor and related structure Electricity 531 Expired
US6093594A CMOS optimization method utilizing sacrificial sidewall spacer Electricity 241 Expired
US6800910B2 FinFET device incorporating strained silicon in the channel region Electricity 218 Expired
US6211044A Process for fabricating a semiconductor device component using a selective silicidation reaction Electricity 161 Expired
US6255169A Process for fabricating a high-endurance non-volatile memory device Electricity 141 Expired
US6657276B1 Shallow trench isolation (STI) region with high-K liner and method of formation Electricity 122 Expired
US6600170B1 CMOS with strained silicon channel NMOS and silicon germanium channel PMOS Electricity 115 Expired
US6465334B1 Enhanced electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors Electricity 113 Expired
US6811448B1 Pre-cleaning for silicidation in an SMOS process Electricity 106 Expired
US7078299B2 Formation of finFET using a sidewall epitaxial layer Emerging Cross-Sectional Technologies 103 Expired
US6797602B1 Method of manufacturing a semiconductor device with supersaturated source/drain extensions and metal silicide contacts Electricity 103 Expired
US6703648B1 Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication Emerging Cross-Sectional Technologies 102 Expired
US6787864B2 Mosfets incorporating nickel germanosilicided gate and methods for their formation Electricity 98 Expired
US6657223B1 Strained silicon MOSFET having silicon source/drain regions and method for its fabrication Electricity 95 Expired
US6555879B1 SOI device with metal source/drain and method of fabrication Electricity 92 Expired
US6955969B2 Method of growing as a channel region to reduce source/drain junction capacitance Electricity 88 Expired
US6479866B1 SOI device with self-aligned selective damage implant, and method Electricity 88 Expired
US6528858B1 MOSFETs with differing gate dielectrics and method of formation Electricity 84 Expired
US6504214B1 MOSFET device having high-K dielectric layer Electricity 83 Expired
US6475874B2 Damascene NiSi metal gate high-k transistor Electricity 76 Expired
US6855982B1 Self aligned double gate transistor having a strained channel region and process therefor Electricity 76 Expired
US6159782A Fabrication of field effect transistors having dual gates with gate dielectrics of high dielectric constant Electricity 75 Expired
US6902991B2 Semiconductor device having a thick strained silicon layer and method of its formation Electricity 68 Expired
US7138302B2 Method of fabricating an integrated circuit channel region Electricity 68 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.