SRAM cell array structure
US7952911B2 · kind B2 · utility
10Cited by
0References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2008 |
| Grant date | May 31, 2011 |
| Priority date | — |
| Expiry date | Jul 4, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention discloses a static random access memory (SRAM) cell array structure which comprises a first and second bit-line coupled to a column of SRAM cells, the first and second bit-lines being substantially parallel to each other and formed by a first metal layer, and a first conductive line being placed between the first and second bit-lines and spanning across the column of SRAM cells without making conductive coupling thereto, the first conductive line being also formed by the first metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.