Secured coprocessor comprising an event detection circuit
US7954153B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2006 |
| Grant date | May 31, 2011 |
| Priority date | — |
| Expiry date | Feb 21, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A coprocessor includes a calculation unit for executing at least one command, and a securization device. The securization device includes an error detection circuit for monitoring the execution of the command so as to detect any execution error, putting the coprocessor into an error mode by default as soon as the execution of the command begins, and lifting the error mode at the end of the execution of the command if no error has been detected, an event detection circuit for monitoring the appearance of at least one event to be detected, and a masking circuit for masking the error mode while the event to be detected does not happen, and declaring the error mode to the outside of the coprocessor if the event to be detected happens while the coprocessor is in the error mode. Application in particular but not exclusively to coprocessors embedded in integrated circuits for smart cards.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.