Semiconductor device with low buried resistance and method of manufacturing such a device
US7956399B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2006 |
| Grant date | Jun 7, 2011 |
| Priority date | — |
| Expiry date | Dec 1, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02E10/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention relates to a semiconductor device (10) with a substrate (11) and a semiconductor body (12) of silicon which comprises an active region (A) with a transistor (T) and a passive region (P) surrounding the active region (A) and which is provided with a buried conducting region (1) of a metallic material that is connected to a conductive region (2) of a metallic material sunken from the surface of the semiconductor body (12), by which the buried conductive region (1) is made electrically connectable at the surface of the semiconductor body (12). According to the invention, the buried conducting region (1) is made at the location of the active region (A) of the semiconductor body (12). In this way, a very low buried resistance can be locally created in the active region (A) in the semiconductor body (12), using a metallic material that has completely different crystallographic properties from the surrounding silicon. This is made possible by using a method according to the invention. Such a buried low resistance offers substantial advantages both for a bipolar transistor and for a MOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.