Adaptive operational transconductance amplifier load compensation
US7956685B2 · kind B2 · utility
1Cited by
20References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 1, 2010 |
| Grant date | Jun 7, 2011 |
| Priority date | — |
| Expiry date | Jun 1, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03J2200/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A buffer varies the size of its output stage in response to a varying capacitive load. The capacitive load may vary in a predictable or a random manner. The buffer includes an operational amplifier having an output stage of multiple transistors, selectively connected in parallel. During operation, data regarding the size of the capacitive load is obtained and used to determine the size of the output stage. In general, as the capacitive load increases, the number of transistors connected in parallel at the output stage also increases.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.