Structures and methods of trimming threshold voltage of a flash EEPROM memory
US7957188B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2009 |
| Grant date | Jun 7, 2011 |
| Priority date | — |
| Expiry date | Jan 16, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3404
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of trimming FET NVM cells in Multi-Level-Cell (MLC) operation is provided. The method comprises (a) applying a first voltage and a second voltage to a control gate and a bulk of the over-programmed FET NVM cell, respectively; and (b) applying a signal to a drain of the over-programmed FET NVM cell for a time period to produce a limited threshold voltage reduction; wherein polarities of the first voltage and the second voltage are opposite to that of the signal. Thus, the charge placement in the storing material could be precisely controlled within a small range of charge state and produce a multi-bits/cell of higher digital storage density.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.