Memory controller with skew control and method
US7957218B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 11, 2009 |
| Grant date | Jun 7, 2011 |
| Priority date | — |
| Expiry date | Dec 3, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1689
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dual data rate (DDR) memory controller and method are provided. The method includes: receiving a first data strobe at a first terminal from a first memory having a first rank; receiving a first data signal at a second terminal from the first memory having the first rank; calibrating the first data signal with the first data strobe to produce a first calibration value; receiving a second data strobe at the first terminal from a second memory having a second rank; receiving a second data signal at the second terminal from the second memory having the second rank; calibrating the second data signal with the second data strobe to produce a second calibration value; determining a final calibration value using the first and second calibration values; and using the final calibration value to time the first data signal and the second data signal during a read operation of the memories.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.