Apparatus and method for reducing memory access conflict
US7958321B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2008 |
| Grant date | Jun 7, 2011 |
| Priority date | — |
| Expiry date | Sep 29, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0607
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are an apparatus and a method of reducing memory access conflict. An apparatus for reducing memory access conflict when a plurality of data processing elements perform simultaneous access to a memory including a plurality of pages, each of which includes a plurality of subpages, the apparatus comprising: an access arbiter mapping a subpage division address corresponding to least significant bits of a memory access address received from each of the data processing elements to another address having a same number of bits as the subpage division address in order for data to be output from each of the subpages in a corresponding page at a time of the simultaneous access; and a selector, prepared for each of the pages, selecting to output one of the data output from the subpages using the mapped results.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.