Memory device for repairing a neighborhood of rows in a memory array using a patch table
US7958390B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2007 |
| Grant date | Jun 7, 2011 |
| Priority date | — |
| Expiry date | Dec 8, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/765
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device for repairing a neighborhood of rows in a memory array using a patch table is disclosed. In one embodiment, circuitry in the memory device is operative to store, in a temporary storage area of the memory device, (i) first data to be stored in row N in the memory array, (ii) second data, if any, stored in row N−1 in the memory array, and (iii) third data, if any, stored in row N+1 in the memory array. The circuitry is operative to write the first data in row N in the memory array, and, in response to an error in writing the first data, to write the first data, the second data, if any, and the third data, if any, in respective rows in a repair area in the memory device. The circuitry is further operative to add the addresses of rows N−1, N, and N+1 to a table stored in the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.