Sublithographic patterning method incorporating a self-aligned single mask process
US7960096B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2008 |
| Grant date | Jun 14, 2011 |
| Priority date | — |
| Expiry date | Dec 6, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32139
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of implementing sub-lithographic patterning of a semiconductor device includes forming a first set of patterned features with a single lithography step, the initial set of patterned features characterized by a linewidth and spacing therebetween; forming a first set of sidewall spacers on the first set of patterned features, and thereafter removing the first set of patterned features so as to define a second set of patterned features based on the geometry of the first set of sidewall spacers; and performing one or more additional iterations of forming subsequent sets of sidewall spacers on subsequent sets of patterned features, followed by removal of the subsequent sets of patterned features, wherein a given set of patterned features is based on the geometry of an associated set of sidewall spacers formed prior thereto, and wherein a final of the subsequent sets of patterned features is characterized by a sub-lithographic dimension.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.