Stress relief of a semiconductor device
US7960814B2 · kind B2 · utility
7Cited by
7References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 8, 2007 |
| Grant date | Jun 14, 2011 |
| Priority date | — |
| Expiry date | Oct 12, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a die including an active region, a scribe region, and a perimeter, wherein the scribe region is closer to the perimeter than the active region. In one embodiment, the die further comprises a crack arrest structure formed in the scribe region, and wherein the crack arrest structure includes one of curva-linear shapes and polygonal shapes concentrically oriented around a common center located at or near at least one corner of the die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.