Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same

US7960836B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Brent A. Anderson · Jericho, US
• Jeanne P. Bickford · South Burlington, US
• Markus Buehler · Holzgerlingen, DE
• Jason D. Hibbeler · Williston, US
• Juergen Koehl · Holzgerlingen, DE
• Edward J. Nowak · South Burlington, US

Key dates

• Filing date: Mar 10, 2008
• Grant date: Jun 14, 2011
• Expiry date: Oct 26, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is substantially axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is substantially axially aligned with the third via. The second, third, and fourth vias, and the third and Fourth wires form a path between the first and second wires redundant to the first via.