Inventor · Holzgerlingen, DE

Markus Buehler

25Patents
4h-index
45Co-inventors
59Inventor score

Filing activity: May 18, 2005 → Mar 31, 2020

Most-cited inventions

PatentTitleAreaCited byStatus
US7308669B2 Use of redundant routes to increase the yield and reliability of a VLSI layout Physics 192 Active
US8234594B2 Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same Electricity 7 Active
US7386815B2 Test yield estimate for semiconductor products created from a library Emerging Cross-Sectional Technologies 6 Active
US7996808B2 Computer readable medium, system and associated method for designing integrated circuits with loop insertions Physics 4 Active
US8015527B2 Routing of wires of an electronic circuit Physics 4 Active
US8010916B2 Test yield estimate for semiconductor products created from a library Emerging Cross-Sectional Technologies 2 Active
US8380737B2 Computing intersection of sets of numbers Physics 2 Active
US7984394B2 Design structure for a redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same Emerging Cross-Sectional Technologies 2 Active
US8010925B2 Method and system for placement of electric circuit components in integrated circuit design Physics 2 Active
US8407654B2 Glitch power reduction Physics 2 Active
US8612911B2 Estimating power consumption of an electronic circuit Physics 1 Active
US7962881B2 Via structure to improve routing of wires within an integrated circuit Physics 1 Active
US8495286B2 Write buffer for improved DRAM write access patterns Emerging Cross-Sectional Technologies 1 Active
US7960836B2 Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same Electricity 1 Active
US7904861B2 Method, system, and computer program product for coupled noise timing violation avoidance in detailed routing Physics 1 Active
US8513663B2 Signal repowering chip for 3-dimensional integrated circuit Electricity 1 Active
US8032851B2 Structure for an integrated circuit design for reducing coupling between wires of an electronic circuit Physics 0 Active
US8731858B2 Method and system for calculating timing delay in a repeater network in an electronic circuit Physics 0 Active
US10831493B2 Hardware apparatus to measure memory locality Physics 0 Active
US8006208B2 Reducing coupling between wires of an electronic circuit Physics 0 Active
US8756538B2 Parsing data representative of a hardware design into commands of a hardware design environment Physics 0 Active
US11281474B2 Partial computer processor core shutoff Physics 0 Active
US8627263B2 Gate configuration determination and selection from standard cell library Physics 0 Active
US9760669B2 Congestion mitigation by wire ordering Physics 0 Active
US7398485B2 Yield optimization in router for systematic defects Physics 0 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.